1. Field of the Invention
The present invention relates to a driver circuit for use in a display device and, more particularly, to a driver circuit adapted for use in an active matrix liquid crystal display.
2. Description of the Prior Art
Heretofore, a driver circuit for use in a display device such as an active matrix liquid crystal display adopted line-sequential scanning making use of shift registers.
The prior art liquid crystal display is schematically shown in FIG. 1. A signal line driver circuit 101 and a scanning line driver circuit 102 are formed on the same glass substrate. Also, a liquid crystal pixel portion 103 is created in the center of the display device.
The driver circuits 101 and 102 are connected with the liquid. crystal pixel portion 103 by signal lines X1, X2, . . . extending in the direction of columns and by signal lines Y1, Y2, . . . extending in the direction of rows. Thin-film transistors (TFTs) acting as switching devices are formed at the intersections of the signal lines and the scanning lines. That is, the TFTs are arranged in rows and columns.
The source electrodes of the TFTs are connected with the signal lines. The gate electrodes are connected with the scanning lines. The drain electrodes are connected with the pixel electrodes, which are located on the opposite side of a liquid crystal material from a counter electrode (not shown).
The signal lines are sequentially scanned by the signal line driver circuit 101. In synchronism with this scanning, signals are supplied to the liquid crystal pixel portion 103 via the scanning lines from the scanning line driver circuit 102. In this way, the signals necessary to provide a display of images are applied to the liquid crystal pixel portion 103.
The line-sequential scanning is now described in detail. One input signal is transmitted with a delay. The signal lines in the scanning line driver circuit are sequentially scanned. Every transistor on one scanning line is once driven into conduction. Signals are supplied to signal storage capacitors via the signal lines from the signal line driver circuit. The supplied signals keep the liquid crystal material activated until scanning for the next frame is started.
At this time, if a constant voltage is kept applied to the liquid crystal material, then it will deteriorate. In order to prevent this from occurring, the polarity of the display signal applied to the liquid crystal material is reversed every frame. In particular, the voltage applied to the source of each TFT forming a pixel is changed from a reference voltage of +10 V to +5 V and from the reference voltage to xe2x88x925 V, and so on.
In the line-sequential scanning method described above, n stages of shift register circuits connected in series are employed to delay signals. The shift register circuits are made up of flip-flops. In the case of the signal line driver circuit, the number of stages n of the connected shift register circuits is the number of pixels in the horizontal direction. In the case of the scanning line driver circuit, the number of stages n is the number of pixels in the vertical direction.
The output signal from the shift register circuits connected in series is sent to the next stage of shift register circuit, delayed, and transmitted. Signal conversion circuits and amplification circuits such as analog memories and inverters are connected in series with the outputs of the shift register circuits.
FIG. 2 is a block diagram of an analog line-sequential driver circuit. This circuit includes a signal line driver circuit 200 and a scanning line driver circuit 201. The signal line driver circuit 200 consists of a shift register circuit composed of flip-flops connected in series. Power voltages Vdd (202) and Vss (203) are applied to the signal line driver circuit 200. Also, clock pulses CP (204) are applied to the signal line driver circuit 200. An applied start pulse SP (205) is passed through the flip-flops with delays in the direction of scanning (e.g., to the right), the flip-flops are connected in series inside. The signal line driver circuit 200.
The shift registers deliver output signals Q0, Q1, . . . , Qn, respectively. Using these output signals as timing signals, a video signal 206 indicating data about gray levels is sampled by a sampling circuit using an analog switch 207.
The sampled data about the gray levels is once stored in an analog memory 208 before being applied to the pixel portion. The stored data is scanned at the timing determined by latch pulses 209 supplied from the outside. The signal is subjected to an impedance transformation in an analog buffer 210. Then, the signal is sent to a pixel TFT 212 through a signal line 211. In each stage of the signal line driver circuit 200, such a signal path is followed. As a result, an image is scanned along the successive lines sequentially.
In recent years, digital memories using latches have been increasingly employed instead of analog memories. That is, data signal is not stored in analog memories but applied to latches, where the image data is retained as a binary-coded digital signal.
By digitizing signals in this way, decreases in the life of gray-level display data, as encountered in the analog configuration, are avoided. Hence, stable gray-level signals can be obtained.
Furthermore, lower voltage and lower electric power consumption can be accomplished by utilizing the digital scheme. This, in turn, leads to lower costs. In addition, the operation speed can be made higher.
However with the prior art display device driver circuit using shift register circuits, if any one of the shift register circuits connected in series is defective, then no signal is transmitted to the following stages of shift register circuits. This causes a decrease in the production yield of the whole display device.
Furthermore signal necessary to provide a display is carried by one video signal, a high voltage is necessitated. As a result, the electric power consumed is increased.
The video signal is passed via Additionally, the sampling circuit to the analog memory (capacitor) and once stored there. Electric charge, however, leaks from this analog memory. Therefore, it may not be possible to store a required amount of electric charge. This shortens the life of the display data signal. As a result, the image quality is deteriorated.
This is especially true, where the driver circuits are made up of TFTs formed on a glass substrate or the like, as these driver circuits occupy a broader area than driver circuits formed on a single-crystal substrate. Therefore, faults are more likely to occur. For this reason, a driver circuit and a liquid crystal display portion are integrally formed on a glass substrate. In the case of an active matrix liquid crystal display incorporating a peripheral circuit, faults tend to occur with the TFTs forming shift registers, thus deteriorating the production yield of the finished display device. As a result, the cost is increased.
In a line-sequential analog driver circuit, every necessary gray-level data is carried by only one video signal. Therefore, a high voltage is needed. This shortens the lifetime of the circuit made up of TFTs. The electric power consumed is inevitably increased.
Where an analog memory is used, there is the possibility that the life of the gray-level display data is shortened due to leakage of electric charge from capacitors. Therefore, it is difficult to accomplish high image quality.
It is an object of the present invention to provide a display device driver circuit which is free of the foregoing problems, has a shortened scanning time, and enables high-speed operation and lower electric power consumption.
It is another object of the invention to provide a driver circuit which is for use in a display device and which permits the display device to be manufactured with higher yield.
One embodiment of the present invention is a driver circuit for use with an active matrix liquid crystal display having switching devices at pixels, said active matrix liquid crystal display having signal lines and scanning lines, said driver circuit receiving data about gray levels, said data being represented in terms of digital values. This driver circuit has an address decoder circuit for selecting desired ones from said signal lines and scanning lines.
Another embodiment of the invention is a driver circuit for use with an active matrix liquid crystal display, said active matrix liquid crystal display having signal lines and scanning lines, said driver circuit receiving data about gray levels, said data being represented in terms of digital values. This driver circuit comprises: an address decoder circuit for selecting signal lines to which said data about gray levels is sent; a gray level-holding circuit for holding said data about gray levels; a gray level-synchronizing circuit for synchronizing timing at which said held data is sent with timing of scanning of said liquid crystal display; and a decoder circuit for selecting gray level potentials to be sent to said signal lines according to said gray level data synchronized by said gray level-synchronizing circuit.
A further embodiment of the invention is a driver circuit for use with an active matrix liquid crystal display, said active matrix liquid crystal display having signal lines and scanning lines, said driver circuit receiving data about gray levels, said data being represented in terms of digital values. This driver circuit comprises: an address decoder circuit for selecting signal lines to which said data is sent; a gray level-holding circuit for holding said data about gray levels in synchronism with an output signal from said address decoder circuit; a gray level-synchronizing circuit for synchronizing timing at which said held data is sent with timing of scanning of said liquid crystal display; and a decoder circuit for selecting gray level potentials to be sent to said signal lines according to said data synchronized by said gray level-synchronizing circuit.
Still another embodiment of the invention is in a driver circuit for use with an active matrix liquid crystal display, said active matrix liquid crystal display having signal lines and scanning lines, said driver circuit receiving data about gray levels, said data being represented in terms of digital values. This driver circuit comprises: an address decoder circuit for selecting signal lines to which said data is sent; a gray level-holding circuit for holding said data about gray levels; a gray level-synchronizing circuit for synchronizing timing at which said held data is sent with timing of scanning of said liquid crystal display; and a decoder circuit for selecting one from a plurality of gray-level potential signals having different voltage values for different gray levels according to the data synchronized by said gray level-synchronizing circuit.
In one feature of the invention, a random access method using an address decoder circuit is adopted instead of the conventional line-sequential scanning method utilizing shift register circuits. The use of the address decoder circuit makes it possible to select addressed signal lines or scanning lines, unlike in the past, where lines have been sequentially specified. In the case of the line-sequential scanning using shift register circuits, one input signal is transmitted with a delay and, therefore, if one circuit becomes defective, the production yield of the finished display device is affected severely.
On the other hand, in the address decoder circuit used in the present invention, if the driver circuit connected with any one signal line or scanning line becomes faulty, driver circuits connected with other signal lines or scanning lines are not affected. Consequently, numerous display devices providing a better display than the prior art construction driven by the line-sequential scanning using shift register circuits can be obtained. As a result, display devices can be manufactured with greatly improved yield.
Furthermore, desired pixels can be randomly accessed. Therefore, the scanning time can be shortened compared with the prior art shift register which scans the successive lines sequentially during each scan. Hence, higher-speed operation can be obtained.
In addition, it is necessary to operate only the circuits which activate the selected signal lines or scanning lines. Therefore, the electric power consumed can be reduced compared with the case in which shift register circuits that are required to operate up to the preceding stage are used.
Other objects and features of the invention will appear in the course of the description thereof, which follows.